SystemVerilog stores each element in long word (32 bits). For example, following declaration will use 32 bits in the memory, although only 8 bits are really used .
Bit [7:0] a;
‘a’ is a single element with 8 bits.The memory use will be as below.
Rewriting the above declaration like following
Bit [7:0] a_unpacked [2:0];
Now 'a' become an array which contains 3 elements with the size of 8 bits each. As ‘SystemVerilog stores each element in a longword (32 bits)’. In the above declaration will look like this
The memory is not used efficiently (not well packed), but sometimes it is necessary to declare this way. It is called unpacked array. Let’s rewrite the above declaration into following way
Bit [2:0] [7:0] a_packed;
The word dimension [2:0] moved next to bit dimension [7:0]. ‘a’ is an element (note it is single element) which has 3 sets of 8 bit words. Since a single element stored in a long word, memory usage will look like this
The memory used efficiently (well packed). It is called packed array.